1. Field of the Invention
The present invention relates to data correlators designed to perform hamming distance correlations on real-time data.
2. Description of the Related Art
Data correlators have been developed which use hamming distance as a measure of correlation between real-time data and a predetermined reference pattern. Data correlators count the number of occurrences of bit matches between a serial input data and a reference data pattern producing a hamming distance correlation value. Such data correlators are effective in applications which require fast correlations between real-time input bit streams and a reference pattern. Such applications include image comparison and recognition, radar/sonar pattern matching, data synchronization, flag word detection, check sorting equipment, bar code identification, video frame synchronization, and time delay measurement systems.
A 64-bit data correlator implementing hamming distance correlation was developed by TRW LSI Products, Inc., La Jolla, Calif., known as the TDC 1023 Digital Output Correlator. The TDC 1023 has an implementation resembling the exemplary circuit diagram shown in FIG. 1. FIG. 1 shows a data correlator 100 which correlates serial input data to stored reference pattern data in real-time. The data correlator 100 receives SERIAL INPUT DATA one bit at a time by serially shifting and latching the SERIAL INPUT DATA into data register 10. The serial shifting and latching are enabled on the transition of a clock-1 signal (not shown). The SERIAL REFERENCE PATTERN DATA is clocked into a temporary reference data register (not shown) one bit at a time by serially shifting and latching on the transition of a clock-2 signal (not shown). The data in the temporary reference data register is latched into reference data register 15 by a LATCH ENABLE signal (not shown). The data correlator 100 receives serial mask data one bit at a time by serially shifting and latching the serial mask data into mask register 20. A threshold register 25 is loaded 7 bits in parallel by an IO bus and latched by a CLOCK-3 (not shown). The hamming distance correlation is performed by the XOR-AND circuit 30. Logic level zero bits in the mask register 20 effectively mask out the results of the hamming distance correlation for those bit positions. The XOR-AND circuit 30 outputs a logic level 1 when a bit of data in the data register 10 is not the same logic value as the corresponding bit of data in the reference data register 15, excluding masked bit positions. A summation circuit 35 sums all of the bits in agreement (e.g., when the hamming distance equal zero) received from the XOR-AND circuit 30, i.e all of the ones from the XOR-AND circuit 30 are added. The summation circuit 35 either can output the sum directly to the 7 bit parallel bus IO or to a comparator 40. The comparator 40 compares the summed value from the summation circuit 35 to a threshold value stored in threshold register 25. The comparator 40 outputs a logic value 1 when the summed value is greater than or equal to the threshold value.
A major limitation of the device of FIG. 1 is that the word size is fixed at 64 bits. To overcome this problem, a 128-bit data correlator implementing hamming distance correlation has been developed by TRW LSI products, known as the TMC 2221 CMOS Programmable Digital Output Correlator. The TMC 2221 has an implementation resembling the exemplary circuit diagram shown in FIG. 2. FIG. 2 shows a 128-bit data correlator 200 with four 32-bit data correlators 100 similar to the 64-bit data correlator shown in FIG. 1. The 32-bit data correlator 100 is the same as 64-bit data correlator 100 except that the 32-bit data correlator 100 has 32 bit registers instead of 64-bit registers. The serial input signals SERIAL DATA IN and SERIAL REFERENCE IN are serially loaded as described for the 64-bit data correlator except the serial data flows from one 32-bit data correlator to the next adjacent correlator 100 until the correlator 100-3 stores the first thirty-two bits of the serial data. Each 32-bit data correlator 100 outputs a correlation value as described for the 64-bit data correlator. The correlation values are summed two at a time by adders 210-0 and 201-1 and then combined in combining matrix 220. The combining matrix 220 outputs the sum of the correlation values on a 8 bit parallel bus RESULTS.
As shown above, the data correlators have a predetermined word size, so a different chip is required when an application requires a different size word to be correlated. This limitation becomes apparent when flexibility in word-length is needed: not only does it become costly to maintain a stock of several different word size chips but also the space required for the additional chips increases the size of the PC board to which the chips are mounted. Further, if the apparatus of FIG. 2 was to be used in a 32-bit configuration mode, correlators 100-1, 100-2 and 100-3 would be disabled, resulting in inefficient use of circuitry.
Finally, the necessity of a different chip to obtain a different size word to be correlated requires the user to make design and programming changes based upon the different protocols for each chip.
It would be desirable to provide a data correlator arrangement which was specifically implemented for high speed real-time data correlation which was user configurable. Specifically, it would be advantageous to allow the user to select a 32-bit, 64-bit or a 128-bit word size data correlator. In addition, if the data correlator is interfaced with a microprocessor, it would be desireable to be able to load all correlation parameter data through the microprocessor bus, except for the serial input data which undergoes bitwise hamming distance data correlation. Finally, it would be desirable if the data correlator arrangement was implemented to allow real-time data correlation at speeds up to 50 MHz, thereby increasing the number of different applications.